1. Field of the Invention
This invention relates generally to high-speed flash analog-to-digital converters (ADCs), and more particularly to a method of background offset cancellation for flash ADCs based on interleaved auto-zero (IAZ) architecture.
2. Description of the Prior Art
Comparators are used in flash ADCs to compare the input voltage with the reference voltage generated by the reference ladder and make a decision based on the relative value of the input voltage with respect to the reference voltage. Differential comparators with frequent auto-zeroing are used for high-speed flash ADCs having 6 or more bits of resolution. The advantages of fully differential schemes include reduced charge injection error, high common-mode signal noise rejection and increased immunity to the power supply and substrate noise. Fully differential comparators are indispensable to achieve high resolution for flash ADCs operating in a mixed-signal environment. The minimum resolution of a comparator is limited by its offset voltage and the low frequency 1/f noise. Techniques such as auto-zeroing serve to cancel the comparator offset, reduce its low frequency 1/f noise and sample the reference levels for comparison with the input. During the comparison phase, the stored reference value is subtracted from the input and the result is amplified by the comparator to output a decision. Auto-zeroing is essential for high-resolution flash ADCs. Typically, a comparator is auto-zeroed every clock cycle by assigning a portion of the clock period for auto-zeroing and the remaining portion for conversion. Frequent auto-zeroing is desirable for obtaining high resolution, but it causes various transient noises, kickback noise to the reference resistor ladder, and power supply noise during the transition from auto-zeroing to comparison and from comparison to auto-zeroing. Further, since there is an auto-zeroing period between two comparison periods, continuous conversion is not possible. Various other problems present in this conventional interleaved auto-zeroing implementation include: 1) Since half of the conversion cycle time is spent on auto-zeroing, only half of the clock period is available for conversion, requiring the comparator circuit to be designed at twice the operating speed; 2) As the frequency of operation increases, the amount of time available for auto-zeroing shortens; 3) Kickback noise occurs on the reference ladder when the comparator is auto-zeroed; and 4) The resistance of the reference ladder is determined by the RC time constant during the auto-zeroing phase for a given sampling capacitor size; and since this time constant is a fraction of the operating clock period, the resistance of the reference ladder depends on the conversion rate.
The foregoing and other like problems restrict high-speed ADC operation and makes it difficult to operate the ADC in a mixed-signal environment. In order to reduce various transient noises and to achieve continuous conversion, it is desirable to reduce the auto-zeroing rate without requiring an extra auto-zeroing period for the whole ADC and to design a high-speed comparator that compares several times with one auto-zeroing.
To meet the above and other objectives, the present invention provides an offset cancellation technique that performs offset cancellation in the background (i.e. without interrupting analog-to-digital conversion) by using one extra comparator slice and by making the auto-zeroing period independent of the operating clock period. The time available for the conversion process is thus extended while the state transition period between auto-zeroing and comparison is reduced. At any instance of time, one comparator is auto-zeroed while the remaining comparators perform A/D conversion.
In one aspect of the invention, a background offset cancellation circuit that employs differential comparators and that is suitable for use with a high-speed flash ADC having 6 or more bits of resolution is implemented to reduce the number of complementary switches necessary to provide reference tap values leading to substantial saving in die area.
In another aspect of the invention, a background offset cancellation circuit that employs differential comparators and that is suitable for use with a high-speed flash ADC having 6 or more bits of resolution is implemented to reduce the series switch resistance and the parasitic junction capacitances in the reference voltage path, improving the settling characteristics of the reference ladder.
In yet another aspect of the invention, a background offset cancellation circuit that employs differential comparators and that is suitable for use with a high-speed flash ADC having 6 or more bits of resolution is implemented to minimize the size and the power consumption of the clock driver(s) necessary to operate the complementary switches associated with setting reference tap values needed for auto-zeroing.
In still another aspect of the invention, a background offset cancellation circuit that employs differential comparators and that is suitable for use with a high-speed flash ADC having 6 or more bits of resolution is implemented to simplify the layout of the comparator slice.
In still another aspect of the invention, a background offset cancellation circuit that employs differential comparators and that is suitable for use with a high-speed flash ADC having 6 or more bits of resolution is implemented to cancel the offsets of the operational amplifier and remove the finite gain error.